Only two wait cycles are inserted when activating CS3 or CS4.
The low-pulse width of RD* and WE* for CS3 and CS4 is 86ns.
In DRAM, the wait cycles cannot be controlled by DWC1 and DWC2.
DWC is a register used to control the wait time for SRAM or ROM etc. in DRAM, the wait time is controlled by DRC0-3.
Four types of wait cycles can be set in the DRC0-3 registers, using the DTC register to specify which DRC should be used in each block.
Check to make sure that the BCT register setting is correct (the corresponding bit is set to 00) in the case of SRAM.