What is the initial level of the TxD pin when the serial I / O mode select bits (SMD 0 to SMD 2) of the UARTi transmit / receive mode register (UiMR) are set to each operation mode?
Both initial levels of the TxD pin output "H" level from the time the clock synchronous serial I / O mode or UART mode is selected by the serial I / O mode select bits (SMD0 to SMD2) until transfer starts. However, when the NCH bit in the UiC0 register is 1 (N channel open drain output), the TxD pin goes into a high impedance state.
|R8C/34E, R8C/34F, R8C/34G, R8C/34H|
|R8C/36E, R8C/36F, R8C/36G, R8C/36H|
|R8C/38E, R8C/38F, R8C/38G, R8C/38H|