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Why reception completion interrupt does not occur on the slave side?

Latest Updated:04/01/2006

Question:

A transmission completion interrupt occurs immediately after transmitting data from the master side (uPD78F9488), but a reception completion interrupt does not occur on the slave side (uPD78F9306).
However, this interrupt does occur on the slave side when data is transmitted from the master side after writing data to SIO10 on the slave side.

Answer:

It could be that communication has not been started on the slave side (by writing dummy data to SIO10) before data is transmitted from the master.
In terms of the communication procedure, first the slave enters the communication ready state, and then the master starts communication. The serial clock is then output from the master and slave data is sent to the master on this clock. At the same time, master data is sent to the slave.
Unless this order is followed, the slave will not operate regardless of how many clocks come from the master.
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